The present application relates generally to a fabrication method of semiconductor memory devices, and more particularly, to a capacitor fabrication method capable of enhancing the capacitance of a capacitor.
The sharp increase of the recent demands for memory devices may be due to the advances in semiconductor fabrication technologies. In a semiconductor memory device, capacitors are generally utilized as the data storage means. The capacitance of a capacitor in a semiconductor device is variable based on the distance between two electrodes and the dielectric constant of a dielectric film inserted in between the two electrodes.
However, as the semiconductor memory devices are highly integrated, the high integration tends to decrease the area for the fabrication of the capacitors and thus leads to the reduced capacitor capacitance because of the decreased electrode area in the semiconductor device.
FIGS. 1A-1D are sectional views illustrating a conventional fabrication method of a capacitor in a semiconductor memory device.
As shown in FIG. 1A, bit lines 3 are formed on a semiconductor substrate 1, and the insulation spacers 4 are formed on the lateral portions of the bit lines 3. Although not shown in the drawings, transistors including the dopant regions for the source/drain and for the gate electrodes are also fabricated on the semiconductor substrate 1. The description relating to the transistor fabrication processes, which may occur before the formation of the bit lines, is omitted here.
Thereafter, several films are formed over the semiconductor substrate 1, the bit lines 3, and the insulation spacers 4 in the order of: an interlayer insulation film 5, a silicon nitride film 6, and a buffer film 7 as shown in FIG. 1A. The buffer film 7 is made from an oxide film of Plasma Enhanced-Tetraethyl Orthosilicate (PE-TEOS) at a thickness of 500 to 1500 xc3x85. Then a pattern of photosensitive film 20 is formed on the buffer film 7 to expose contact areas (not shown in FIG. 1A) for etching. The buffer film 7, silicon nitride film 6, and the interlayer insulation film 5 are etched according to the photosensitive film pattern as a mask to form contact holes h1 as shown in FIG. 1B. The photosensitive film pattern 20 is then removed.
A first polysilicon film is formed on a resultant structure including inside the contact holes h1, and then an etch-back or a Chemical Mechanical Polishing (CMP) is performed on the first polysilicon film to form conductive plugs 8 in the contact holes h1.
Then, as shown in FIG. 1C, a capacitor oxide film 9 such as a PE-PEOS or PSG film is formed on the resulting surface of the conductive plugs 8 and the buffer film 7. A second polysilicon film 10 is formed on the oxide film 9 as a hard mask. A photosensitive film pattern (not shown) that defines a capacitor area is then formed on the second polysilicon film 10.
The second polysilicon film 10 and the capacitor oxide film 9 are then etched by using the photosensitive pattern (not shown) as an etching barrier, up to the extent that the conductive plugs 8 are exposed in order to form contact holes h2 for forming storage node electrodes (shown as 11a in FIG. 1D). Then, a third polysilicon film 11 (which is used for forming the storage node electrodes shown as 11a in FIG. 1D) is formed on the surface of the resultant structure as shown in FIG. 1C.
Now referring to FIG. 1D, an etch-back or a CMP is performed on the third polysilicon film 11, which covers the walls of the contact holes h2, so that the storage node electrodes 11a are formed in the shape of cylinders on the conductive plugs 8.
The second polysilicon film 10 (FIG. 1C) used for a hard mask and the oxide film 9 (FIG. 1C) are removed. Then, a Ta2O5 dielectric film 12 and a TiN upper electrode 13 are sequentially formed on the storage node electrodes 11a. In order to reduce the contact resistance of the memory cell and the surrounding areas, the resultant structure including the capacitor TiN upper electrode 13 is heat treated at the temperature of 800-900xc2x0 C. (14).
Fabrication of a semiconductor capacitor adopting a fine wiring process of 0.13 xcexcm or less requires that the capacitor height be of at least 15,000 xc3x85 in order to enhance the active area of the storage node electrodes.
However, because the conventional fabrication method as described above deposits the oxide film as the buffer film 7 over the silicon nitride film 6, deposits the silicon nitride film 6 as the etch stopper on the interlayer insulation film 5, and then etches the above deposited films 5, 6, and 7 to form the contact holes h1, the conductive plugs 8 extends over the silicon nitride film 6 by a thickness of 500 to 1500 xc3x85. This reduces the area of the storage node electrodes 11a in proportion to their thickness, while increasing the frequency of bridges between adjacent conductive plugs 8, and causes electrical defects.
Also, in the fabrication method of the prior art, the Critical Dimension (CD) at the inner bottom of a cell is not ensured as a desired sufficient value after a mask process for formation of the storage node electrodes. As a result, after formation of the third polysilicon film 11 for storage node electrodes 11a and during formation of the Ta2O5 dielectric film 12 and the TiN upper electrode 13, step coverage defects may occur, thereby increasing leakage current from the capacitor.
Furthermore, the prior art method described above performs high temperature heat treatment at 800 to 900xc2x0 C. after formation of the TiN upper electrode 13 of the capacitor so that oxidation occurs in the interface between the TiN upper electrode 13 and the Ta2O5 dielectric film 12 during the heat treatment and oxygen vacancies are formed in the Ta2O5 dielectric film 12. This causes the deterioration of the Ta2O5 dielectric film 12 and degrades the dielectric properties of the Ta2O5 dielectric film 12, while Clxe2x88x92ions remaining in the upper electrode TiN film 13 causes the worsened leakage current of the capacitor.
Accordingly, an embodiment of the present invention has been made to solve the above-mentioned problems occurring in the prior art, and an object of the present invention is to provide a capacitor fabrication method in which conductive plugs are prevented from being erected over a silicon nitride film to increase the area of storage node electrodes thereby enhancing the capacitance of a capacitor.
Another object of the invention is to provide a capacitor fabrication method which can ensure the CD at the inner bottom of a memory cell to a desired sufficient value during formation of contact holes for storage node electrodes to improve the step coverage of a Ta2O5 dielectric film and a TiN upper electrode.
Yet another object of the invention is to provide a capacitor fabrication method which can perform low temperature heat treatment to prevent dielectric property degradation of the Ta2O5 dielectric film while reducing the ratio of Clxe2x88x92ions remaining within the upper electrode TiN film thereby preventing leakage current from a capacitor.
In order to accomplish this object, a capacitor fabrication method according to an embodiment of the present invention comprises the following steps. A semiconductor substrate including at least one conductive plug is provided. A silicon nitride film and double capacitor oxide films are formed on the surface of the substrate having at least one conductive plug. The double capacitor oxide films have different wet etch rates. Dry etching and wet etching are sequentially performed to the selected portions of the double capacitor oxide films. Using the silicon nitride film as an etch stopper, at least one contact hole is formed by etching until the conductive plug is exposed. The contact hole is used for forming a storage node electrode. A silicon film for storage node electrode and a filler film in their order on a resultant surface of the substrate having the contact hole. The filler film and the silicon film are then etched in the selected portions to form a storage node electrode until surfaces of the double capacitor oxide films are exposed to form a cylindrical storage node electrode. The remaining filler film and the double capacitor oxide films are sequentially removed. A Ta2O5 dielectric film covering the storage node electrode and a TiN film for an upper electrode are then sequentially formed.
Preferably, the silicon nitride film is formed using Low Pressure Chemical Vapor Deposition (LP-CVD) or Plasma Enhanced Chemical Vapor Deposition (PECVD) at a thickness of 200 to 1000 xc3x85.
The double capacitor oxide films preferably include a first capacitor oxide film of any one selected from a group including Phospho-Silicate-Glass (PSG), Boro-Phosphor-Silicate Glass (BPSG), Low Pressure Tetra-Ethyl-Ortho-Silicate (LP-TEOS), and a second capacitor oxide film of Plasma Enhanced Tetra-Ethyl-Ortho-Silicate (PE-TEOS). The first capacitor oxide film preferably has the wet etch rate that causes the first capacitor oxide film to be etched faster than the second capacitor oxide film.
Preferably, etch selectivity of the double capacitor oxide films to the silicon nitride film-is maintained in a range of 5 through 20:1.
Preferably, the dry etching of the double capacitor oxide films is performed to an over-etch target for 10 to 100%.
The wet etching of the double capacitor oxide films preferably makes use of any one of an HF solution to which H2O2 and ultra pure water are added and an HF/NH4F mixture solution to which H2O2 and ultra pure water are added, as a wet etch solution.
In the method according to an embodiment of the invention, the step of forming a silicon film for a storage node electrode is comprised of the following sub-steps. A primary deposition of a polycrystalline silicon film is performed on the surface of the substrate including the contact hole for a storage node electrode. The polycrystalline silicon film is doped with dopants at a first thickness, and the first thickness is 30 to 70% of the thickness of the storage node electrode. A secondary deposition of a silicon film which is not doped with amorphous dopants is then performed at a second thickness on the polycrystalline silicon film doped with dopants. The sum of the first thickness and the second thickness is the thickness of the storage node electrode. Heat treatment is then performed to the resultant structure to grow Hemi-Spherical Gains (HSGs) to a radius of 50 to 300 xc3x85.
Preferably, the silicon film for a storage node electrode is formed at the thickness of 200 to 600 xc3x85, and the step of etching the silicon film for a storage node electrode is performed to the over-etch target of 5 to 10%.
Preferably, the fill film makes use of any one of a photosensitive film and Undoped Silicate Glass (USG) film.
Preferably, the method of the invention may further comprise the step of performing thermal doping treatment under an atmosphere of phosphorus gas (1 to 5% PH3/N2 or PH3/He) after the step of forming a silicon film for a storage node electrode.
It is preferred that the step of thermal doping treatment is performed in a furnace at a temperature of 600 to 700xc2x0 C. under a pressure of 1 to 100 torr for 30 to 120 minutes.
Preferably, the method of the invention may further comprise the step of performing Rapid Thermal Process (RTP) to the substrate including the silicon film for a storage node electrode at a temperature of 700 to 950xc2x0 C. for 10 to 100 seconds, prior to the step of thermal doping treatment.
The method according to an embodiment of the invention may preferably further comprise the following steps. After performing the step of forming a Ta2O5 dielectric film, primary heat treatment of the substrate including the Ta2O5 dielectric film is performed to remove carbon impurities and oxygen vacancies in the Ta2O5 dielectric film. After performing the step of forming the Tin film for an upper electrode, a secondary heat treatment is performed in situ the surface of the resultant structure to remove Cl ions from the TiN film for an upper electrode.
Preferably, the method according to an embodiment of the invention may further comprise the step of performing nitrification in a furnace or using plasma at a temperature of 400 to 700xc2x0 C. under an NH3 atmosphere, prior to forming the Ta2O5 dielectric film.
Preferably, the primary heat treatment is performed at a temperature of 600 to 800xc2x0 C. under an atmosphere of N2O or O2.
Preferably, the method of the invention may further comprise the steps of performing RTP of the substrate under an atmosphere of O2 (10 to 200 sccm) and N2 (1 to 10 slm), before or after the primary heat treatment.
Preferably, the step of forming a TiN film for an upper electrode comprises forming a first TiN film by CVD and forming a TiN film on the first TiN film via sputtering.
These and various other features as well as advantages which characterize the present invention will be apparent from a reading of the following detailed description and a review of the associated drawings.